1. Field of the Invention
This invention relates generally to buffer circuits and, more particularly, to an interface circuit for use in conjunction with either a synchronous bus system or an asynchronous bus system.
2. Description of the Prior Art
Generally speaking, all signals within a local digital system are controlled by a local clock. Such a system is referred to as a synchronous system. However, when a synchronous system interfaces with a common bus (e.g. data, addresses, control signals, etc.), the bus may either be synchronized with the local clock signal or it may be asynchronous with respect to the local clock signal. If the bus is synchronous, then there are specific timing and phase requirements which must be met in order to complete a transfer operation. If the bus is asynchronous, it is usually necessary to synchronize all signals with the local clock signal. Furthermore, it is generally necessary that a handshake or acknowledge signal be generated at the end of a transfer operation to signify its completion. As a result of these requirements, different circuits are generally required to accommodate synchronous and asynchronous bus systems.